The present invention relates generally to low voltage op-amp circuits that utilize one or more metal oxide semiconductor field effect (MOSFET) shunt switches to couple key circuit nodes together. More particularly, the present invention relates to the design of low voltage operational amplifier circuits with switched capacitor elements.
A variety of desirable complimentary metal oxide semiconductor (CMOS) operational amplifier (xe2x80x9cop-ampxe2x80x9d) circuits are well-known in the field of analog and digital circuit design. These include a variety of CMOS op-amp circuits with switching elements composed of metal oxide semiconductor field effect transistors (MOSFETs). There are many applications where the switching elements are operated in either an xe2x80x9conxe2x80x9d or xe2x80x9coffxe2x80x9d mode to regulate or control other circuit elements. In addition to digital circuit applications, a variety of op-amp circuits incorporate a plurality of switching elements. In the context of operational amplifier circuits, MOSFET switches are used, for example, to couple other impedance elements (e.g., capacitors) to input or feedback paths of an op-amp. MOSFET switches are also used to perform a reset function in op-amp circuits.
At typically power supply voltages of three-to-five volts, MOSFET switches can be modeled as having a sufficiently low enough on-resistance that their non-ideality can be ignored in analyzing the operation of many circuits. An ideal switch has a infinite conductance (zero resistance) in its on-state and zero conductance (infinite resistance) in its off-state. At conventional power supply voltages MOSFET switching elements are often modeled as performing a shunt-switch function because the MOSFET switch has a resistive impedance that is sufficiently small that a negligible voltage drop occurs across the switch.
The design of CMOS op-amp circuits that operate at a low power supply voltage presents special design problems. Low voltage CMOS circuit design is generally considered to include CMOS circuits operating at a supply voltage below about three volts, corresponding to the power supply voltage of current high performance microprocessors. Some consumer electronic devices currently operate at even lower power supply voltages. Miniature hearing aids, in particular, typically have a power supply comprising a single miniature battery with a nominal voltage of about 1.5 volts, corresponding to the voltage of a single miniature electrolytic cell. Although hearing aids are one of the most common CMOS circuits presently designed to be powered by a 1.5 volt power supply, a variety of other compact electronic devices may ultimately be reduced to a size where they will be powered by a single miniature battery.
Referring to FIG. 1A, a general problem in low voltage circuit design is that of a circuit element 105 (shown in phantom) requiring a shunt switch 110 comprised of one or more MOSFET transistors, such as an n-channel MOSFET transistor 115 and a p-type MOSFET transistor 120 forming a transmission gate shunt switch 110. An ideal switch has an infinite conductance (zero-resistance) in its on-state and an infinite resistance (zero conductance) in its off state. However, in low voltage circuit design the switch 110 typically has a significant resistance in its on-state. Additionally, in its xe2x80x9coffxe2x80x9d state, the low voltage switch 110 may also act as a parasitic current/voltage source, altering the voltage at circuit nodes 125, 130 coupled to the shunt switch. In many low-voltage op-amp circuit applications, the non-ideal characteristics of shunt switch 110 degrades the performance of circuit elements 105 coupled to shunt switch 110.
It is difficult at a low power supply voltage to operate a MOSFET switch with both a low on-resistance and acceptable turn off-behavior (e.g., low parasitic turn-off charge injection). CMOS switches, when driven with 3.0 V to 5.0 V gate drive signals, may be readily operated in a so-called xe2x80x9cohmicxe2x80x9d region in which the transistors of the switches have a low on-resistance. The ohmic region of an n-channel MOSFET is typically defined as occurring at a voltage for which the gate-source voltage, VGS, of the MOSFET is greater than the drain-source voltage, VDS, plus a threshold voltage, VTN, or VGS greater than VDS+VTN. In the ohmic region, the source-drain current, IDS, is proportional to the square of the gate-source voltage minus the threshold voltage, or IDS=k(VGSxe2x88x92VTN)2, where k is a constant. For a gate-source voltage above the threshold voltage but below the ohmic region, an n-channel MOSFET operates in a so-called linear or triode region where the drain source voltage increases linearly with drain source voltage, which is expressed mathematically as: IDS=2k[(VGSxe2x88x92VTN) VDSxe2x88x920.5 VDS 2]. The on-resistance, RDS, is very high in the linear region, and is given by the expression: RDS=xc2xdk[(VGSxe2x88x92VTN)xe2x88x920.5 VDS], where k is a constant proportional to the width of the transistor.
A p-channel MOSFET has a similar triode and ohmic behavior but with reference to different voltage polarities. A p-channel MOSFET enters the triode region when the source-gate voltage VSG is greater than a (positive) threshold value, VTP and the source-drain voltage, VSD is less than the source-gate voltage minus the threshold value, which is expressed as: VSD less than VSGxe2x88x92VTP. The corresponding p-channel drain current is: ISD=2k[(VSGxe2x88x92VTP) VSDxe2x88x920.5 VSD 2] and the corresponding on-resistance is: RSD=xc2xdk[(VSGxe2x88x92VTP)xe2x88x920.5 VSD].
FIG. 1B shows the on-resistance of shunt switch 110 as function of input signal level for a constant supply voltage. The resistance of n-channel MOSFET 115 and p-channel MOSFET 120 is shown along with the parallel resistance of switch 110 as a whole. FIG. 1B is for one selection of drain-source voltage. More generally, a family of curves must be drawn for the on-resistance as function of both source-drain voltage and gate-source voltage (PH1 and PH2 in FIG. 1A). For source-drain and gate voltages corresponding to an on-state in the triode region of an individual MOSFET 115, 120, the conductance per unit of gate width is low. Consequently, the gate width of each MOSFET transistor may have to be hundreds of microns wide to have a reasonable on-resistance of switch 110. However, increasing the gate width is not a viable solution in many low voltage circuit designs. One problem is that large area shunt switches 110 increase the size, and hence the cost, of a circuit. Another problem is that increasing the gate width of MOSFET switches 115, 120 increases the non-ideality of switch 110 in regards to its turn-off behavior.
Parasitic charge injection and capacitive feedthrough are the two main deleterious effects which occur in wide gate width MOSFETs at turn off. Since both parasitic charge injection and capacitive feedthrough increase with gate width, increasing the gate width of a MOSFET switch to reduce its on-resistance results in the tradeoff that parasitic charge injection and capacitive feedthrough increase in the off-state.
Parasitic charge injection is, as its name implies, the undesired injection of charge from a MOSFET as it is turned-off. When MOSFET transistors are turned off, channel charge must flow out from the channel region of the transistor to the drain and source junctions. This causes parasitic charge injection every time the switch 110 is turned off. The total channel charge in a n-channel MOSFET increases with gate width and is typically expressed mathematically as: QCH=WLCOX(VGSxe2x88x92VTN), where QCH, is the channel charge, W is the gate width, L is the gate length, and COX is the oxide capacitance. A similar expression also describes to describe the total charge in an p-channel MOSFET but with different polarity of charge, p-type threshold voltage, and source-gate voltage. In a complementary pair switch configuration, such as that of shunt switch 110, the parasitic charge injection of the n-channel transistor tends to act to cancel the parasitic charge injection of the p-channel transistor. However, it is difficult, particularly at a low drain-source voltage, to precisely match the characteristics of the n-channel transistor 115 and p-channel transistor 120 to achieve low net parasitic charge injection. Capacitive feedthrough, as its name implies, is associated with the a capacitive voltage coupling effect caused by the gate-drain capacitance of a MOSFET. The effect of capacitive feedthrough is to form a capacitive voltage divider between the gate-drain (source) capacitance and the load capacitance. When the switch 110 is turned off (low gate voltage) a portion of the gate-signal appears across the load. Since gate-drain capacitance increase with gate width, MOSFETs with a wide gate width have increased capacitive feedthrough.
One important class of circuits for which the non-ideality of MOSFET switches hinders the implementation of low-voltage circuits is switched capacitor op-amp circuits. Generally speaking, in a switched capacitor op-amp circuit two or more branches of the op-amp circuit incorporate a quasi-resistive element comprising a combination of capacitors and switches. FIG. 2(a) shows a prior art switched capacitor circuit element used in a variety of switched capacitor op-amp circuits. Each time the switch(es) open and close there is a change in charge, xcex94Q, associated with a voltage differential, xcex94V, across each capacitor with a capacitance, C, of: xcex94Q=Cxcex94V. If the switch is substantially ideal, its impedance can be ignored so that the time average current passing through the switched capacitor is: I=C(V1xe2x88x92V2)/T, where (V1xe2x88x92V2) is the voltage across the capacitor and the switch and T is the clock period. As shown in FIG. 2(b), for the case of a single capacitor in series with a single ideal switch, the equivalent resistance is Req=1/Cfs, where fs is the switching frequency and C is the capacitance. As indicated in FIG. 2(a) typically two switches are used to control the injection of charge into and out of the switched capacitor. Typically, the two switches are driven by so-called non-overlapping clock signals, as indicated in FIG. 2(c), since this provides superior control over the charge entering and leaving the capacitor. The non-overlapping clock signals may be generated by a variety of means, such as by the modified data flip-flop of FIG. 2(d) that utilizes delay elements to convert an input oscillator signal into two output signals that are complementary and non-overlapping.
A switched capacitor op-amp circuit offers several potential benefits. One benefit is that the equivalent resistance of the branches of a switched capacitor circuit can, in principle, be accurately controlled by selection of the value of the capacitance of the capacitors and the switching frequency. Another potential benefit of a switched capacitor op-amp circuit is that a compact switched capacitor element eliminates the need for large value discrete resistors. For example, an op-amp feedback amplifier design requiring resistive elements with an impedance on the order of several MegaOhms can not readily be implemented with conventional integrated circuit resistors. However, switched capacitor elements can be used to emulate the function of large-value resistors which would otherwise require discrete resistors, thus reducing the cost and size of the op-amp feedback amplifier.
Unfortunately, many of the potential benefits of switched capacitor circuits cannot be realized at a low power supply voltage because of the non-ideality of the switching transistors. A high on-resistance of the switches may compromise the performance of the switched capacitor circuit in a variety of ways. A high on resistance (e.g., an on-resistance greater than about 1% of the desired equivalent resistance) deleteriously affects the ability to accurately control the equivalent resistance of the switched capacitor circuit. Additionally, the settling time of the circuit, i.e., the time required by the circuit to reach a quasi-steady state in response to a sudden change in inputs is a further consideration. If the on-resistance it too high, the RC time constant may be a significant fraction of the on-time (i.e., greater than 10% of the on-time) so that the switched capacitor does not fully charge/discharge during each switching period. On the other hand, if the transistor switches are made wide (e.g. one-hundred microns) to reduce the on-resistance, parasitic charge injection and capacitive feedthrough increase. It is well known in the art of CMOS design that parasitic charge injection and capacitive feedthrough alter the potential at key switched capacitor circuit nodes in a variety of undesirable ways. In switched capacitor filters, for example, parasitic charge injection results in distortion of an analog signal. In the context of miniature low-voltage hearing aids, the aforementioned problems make it impractical with conventional techniques to incorporate a high performance switched capacitor op-amp filter with acceptable sound quality into a hearing aid.
The non-ideality of MOSFET switches at low power supply voltages hinders the implementation of a variety of low-noise op-amp circuits that are compact and consistent with the power supply parameters of a miniature hearing aid battery (e.g., a battery voltage of about 1.5 volts and a low total current consumption). Although switched capacitor op-amp filter circuits for use in hearing aids are one important class of circuits, a variety of other low-voltage circuits may be deleteriously affected by the same problem of the non-ideality of MOSFET shunt switches operated at a low power supply voltage. This includes a variety of low-voltage audio amplifier circuits incorporated into cellular phones, miniature recorders, and other devices incorporating audio devices.
What is desired is a new design approach for designing MOSFET shunt switches for use in CMOS switched capacitor circuits powered by a low voltage power supply.
The present invention generally comprises a low voltage circuit design approach in which a transient voltage pulse multiplier is used to increase the voltage of control signal pulses to key MOSFET switching transistors, enabling them to be sized small enough to have reduced parasitic charge injection and capacitive feedthrough. The present invention is particularly well-suited to a variety of low voltage op-amp circuit having one or more shunt switches, such as switched capacitor op-amp circuits.
The present invention generally comprises a compact, CMOS integrated circuit, having: a DC power supply voltage terminal; a ground terminal; a pulsed signal input node; an integrated capacitor; a MOSFET charging switch, the MOSFET charging switch coupling the capacitor to the DC power supply voltage terminal; a pulsed signal output node; a control circuit to adjust the operation of the MOSFET charging switch so that the capacitor is charged in the absence of a signal at the pulse signal input node whereas the voltage of the capacitor is added in series to the voltage at the power supply terminal in response to input signal pulses at the pulsed signal input to produce voltage multiplied pulses at the pulsed signal output node having an amplitude substantially greater than the power supply voltage; a circuit element with two shunt terminals for electrically coupling two circuit nodes of said circuit element, the circuit element having power supply connections to the DC power supply voltage terminal and said ground terminal; a n-channel MOSFET transistor shunt switch with source and drain terminals coupled to the shunt terminals of the circuit element and a gate terminal coupled to the pulsed signal output node; wherein the gate width of the n-channel MOSFET transistor shunt switch is selected to couple the circuit nodes with a voltage drop of less than ten percent and said MOSFET transistor shunt switch is sized to reduce parasitic charge injection and capacitive feedthrough of the shunt switch.